Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware for a computer system can typically be stored in flash memory devices as well.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are coupled by rows to word lines and their drains are coupled to column bit lines. The source of each floating gate memory cell is typically coupled to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line coupled to their gates. The row of selected memory cells couple stored data values on respective column bit lines by providing differing current characteristics between the coupled source line to the coupled column bit lines corresponding to a programmed state or unprogrammed state.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix having the gates of each floating gate memory cell of the array coupled by rows to word lines. However, each memory cell is not directly coupled to a source line and a column bit line. Instead, the memory cells of the array are arranged together in “strings,” typically of 16 to 32 memory cells each, where the memory cells in the string are coupled together in series between a common source line and a column bit line. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. In addition, the word lines coupled to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage in order to operate them as pass transistors to allow them to pass current in a manner that is unrestricted by their respective stored data values. Under this condition, current flows from the source line to the column bit line through each floating gate memory cell of the series coupled string, restricted only by the memory cells of each string that are selected to be accessed. As a result, the current encoded stored data values of the row of selected memory cells are coupled to the column bit lines.
FIG. 1 illustrates a conventional flash memory device 100. The flash memory device 100 has a NAND flash memory architecture. The memory device 100 includes an address interface 104, a control interface 106, and a data interface 108 through which address and control signals are received by the memory device 100 and through which data is received and provided. The flash memory device 100 further includes a control state machine 110 that directs the internal operation, such as managing the flash memory array 112 and updating RAM control registers and non-volatile erase block management registers 114. The RAM control registers 114 are utilized by the control state machine 110 during operation of the flash memory 100. The flash memory array 112 contains a sequence of memory banks or segments 116. Each memory bank 116 is organized logically into a series of erase blocks (not shown). Memory addresses are received on the address interface 104 of the flash memory 100 and divided into a row and column address portions. In response to a read access, the row address is latched and decoded by row decoder circuits 120, which select and activate a row page (not shown) of memory cells across a selected memory bank. As previously described, a row of memory corresponding to the row address is selected and the bit values encoded in the output of the selected row of memory cells are coupled from a local bit line (not shown). Sense amplifiers 122 associated with a respective memory bank 116 are coupled to the global bit line to detect the encoded bit values of the selected row of memory cells. The column address portion of the memory address is latched and decoded by column decoder circuit 124. The column decoder circuit 124 selects the desired column data from the internal data bus 125 that is coupled to the outputs of the individual read sense amplifiers 122. The column data are coupled to the data buffer 126 for transfer from the memory device through the data interface 108. On a write access the row decoder circuits 120 select the row page and the column decoder circuit 124 selects sense amplifiers 122. Data values to be written are coupled from the data buffer 126 via the internal data bus 125 to the sense amplifiers 122 selected by the column decoder circuit 124, and are written to the selected floating gate memory cells (not shown) of the memory array 112. The written cells are then reselected by the row and column decode circuits 120, 124 and sense amplifiers 122 in order to verify that the correct values have been programmed into the selected memory cells.
NAND flash memory devices are becoming popular due to the high memory densities possible at a relatively low cost. Additionally, NAND flash memory devices generally have faster program and erase times compared to NOR flash memory devices. However, a disadvantage of NAND flash memory devices compared with NOR flash memory devices is that the access time for a random access, or initial access, to the memory array is considerably longer than for a NOR flash memory device. Currently, the initial access time for a NAND flash memory device can be as much as several hundred times longer than for a NOR flash memory device. Although access times for serial accesses subsequent to the initial access are on par with NOR flash memory devices, it is still desirable to reduce the initial access time of a NAND flash memory because of the considerable time required for the initial access.
One factor that contributes to the long random access time of NAND flash memory devices is signal line impedance of word lines. As previously discussed, in accessing a row of memory cells in a NAND flash memory device, the word lines of a block of memory are driven to a relatively high voltage, except for the word line corresponding to the row being accessed. In contrast, accessing a row of memory in a NOR flash memory architecture is accomplished by driving only the word line corresponding to the row of memory being accessed. Due to the line impedance of the word lines, driving a plurality of word lines to a sufficiently high voltage in a NAND flash memory device can take considerable time. FIG. 2A illustrates a conventional layout 200 for a memory array 202 of NAND memory cells, row decoder circuits 204, and driver circuits 206. The row decoder circuits 204 decode address signals to select a row to be accessed, and the driver circuits 206 couple the word lines of the block of memory having the row to be accessed to respective global word lines 210 that carry a voltage level sufficient to drive the word lines of the block of memory. As shown in FIG. 2A, the array of NAND memory cells is arranged as 2,048 blocks of 32 word lines. The word lines extend across 32,768 (32K) bit lines, each bit line representing a column of memory cells. During an access operation, each word line in a block of memory, except for the word line corresponding to the row being accessed, must be driven along its entire length to a relatively high voltage level to perform the access operation.
Reducing the impedance of the word lines is one approach to improving the time required to drive the word lines of a block of memory. One approach is to change the physical properties of the word lines to have a lower impedance for the same length of word line. However, constraints in fabricating the NAND flash memory array often limit these design options. Another approach is to physically change the layout of the array of NAND memory cells, the row decoder circuits, and the driver circuits. FIG. 2B illustrates an alternative layout 250 that reduces the line impedance the each driver circuits 256A, 256B by changing the length of word line each driver circuit must drive. Although the layout illustrated in FIG. 2B has the same memory array capacity as shown in FIG. 2A, namely, 2,048 blocks of 32 word lines, and 32K bit lines, the array of NAND memory cells are divided into two memory sub-arrays 252A, 252B. Each memory sub-array 252A, 252B has half of the bit lines in comparison to the memory array 202 of FIG. 2A, with the word lines of each memory sub-array 252A, 252B being half as long (extending over 16K bit lines) as the word lines of the layout in FIG. 2A.
As with the layout 200 in FIG. 2A, the layout 250 includes only one set of row decoder circuits 254 for selecting the row to be accessed. However, in order to access the same number of columns of NAND memory cells as in the layout 200 of FIG. 2A, two sets of drive circuits 256A, 256B and global word lines 260A, 260B are included to drive a block of word lines in the first memory sub-array 252A and in the second memory sub-array 252B concurrently. Each drive circuit 256A, 256B drives the word lines of the respective memory sub-arrays 252A, 252B. Two sets of drive circuits 256A, 256B are used to avoid the need to form signal lines connecting the word lines of the left and right memory arrays 252A, 252B to a single set of drive circuits. Due to the density of circuits for the row decoder circuits 254, including signal lines that span the region of the row decoder circuits 254 to connect word lines of the two memory sub-arrays 252A, 252B significantly increases circuit layout complexity. In some semiconductor architectures, for example, those using polysilicon word lines, and first and second levels of metal signal lines, it is infeasible to connect two sets of word lines to one set of driver circuits using polysilicon or metal lines. Thus, in order to implement a dual-array layout, and at the very least, reduce circuit layout complexity, two sets of drive circuits 256A, 256B are used, as shown in FIG. 2B.
By reducing the length of the word lines in the layout 250 of FIG. 2B, and providing two sets of driver circuits 256A, 256B, the line impedance driven by each of the driver circuits 256A, 256B is approximately half as much as compared to the layout 200 of FIG. 2A. However, although the layout 250 of FIG. 2B provides the benefit of reducing line impedance for the driver circuits 256A, 256B, the inclusion of another set of drive circuits and global word lines will result in greater die size and increased fabrication complexity to accommodate the extra circuitry. Both results are undesirable and may be unacceptable in applications where reducing chip size and reducing fabrication complexity are priorities.
Therefore, there is a need for an alternative approach to reducing word line impedance in a flash memory device having a NAND flash memory architecture.